1. Technical Field
The present invention generally relates to computer systems and, in particular, to techniques for identifying the characteristics of pluggable computer components.
2. Description of the Related Art
A typical computer is highly modular. During a computer's useful life, one or more components are replaced either due to maintenance or system upgrades. To this end, most computer components are now designed to be "field replaceable."
The process of identifying the characteristics of field replaceable or so-called "pluggable" computer components, such as memory cards, is a long-standing problem in the computer industry. Such characteristics may include, without limitation, such information as where the card was built, the name of the manufacturer, what type of devices reside on the card, their operating characteristics, and so forth. Thus, for example, when a pluggable is first installed in a system, this so-called "vital product data" (VPD) is read (e.g., on power on) by a VPD detection mechanism to identify and catalog the new system component.
Vital product data detection systems handle this identification task typically by employing either a parallel or serial read approach. In the parallel approach, a predetermined set of so-called "physical descriptor" (PD) pins or contacts at the edge of the pluggable card were assigned to be either open (high impedance) or ground, thus forming a "code" to be read by a control chip. The result was a large number of signal pins on a memory controller dedicated to a single function, namely, to determine if a particular PD bit was `0` (grounded on the memory card) or `1` (connected to high voltage (Vcc) via a resistor on the system board). It is also known to have multiple pluggable component devices share the same PD bus and be separately enabled using a buffering technique.
In the serial read approach, a memory device, such as a serial-controlled ROM is used to store the vital product data. A well-known technique uses a National Semiconductor NM34C02 EEPROM to store up to 2048 bits of information. Data transfer between the memory controller to the serial ROM is accomplished through the use of a clock and serial data pin.
These prior art VPD approaches have several problems. One problem with the parallel read technique (i.e. enable PD) is that the buffer is too large to fit on many types of pluggable components, for example, the next generation of DIMM modules that are already fully-loaded with memory devices. More problematic, systems that use one method of VPD collection, e.g., enabled PD with a buffer, are incompatible with systems that use a serial approach. As a result, in the prior art, component design was tailored to the VPD scheme being used.
The present invention addresses these problems.